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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct161 presettable synchronous 4-bit binary counter; asynchronous reset for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 features synchronous counting and loading two count enable inputs for n-bit cascading positive-edge triggered clock asynchronous reset output capability: standard i cc category: msi general description the 74hc/hct161 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct161 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting. synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (cp). the outputs (q 0 to q 3 ) of the counters may be preset to a high or low level. a low level at the parallel enable input ( pe) disables the counting action and causes the data at the data inputs (d 0 to d 3 ) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for pe are met). preset takes place regardless of the levels at count enable inputs (cep and cet). a low level at the master reset input ( mr) sets all four outputs of the flip-flops (q 0 to q 3 ) to low level regardless of the levels at cp, pe, cet and cep inputs (thus providing an asynchronous clear function). the look-ahead carry simplifies serial cascading of the counters. both count enable inputs (cep and cet) must be high to count. the cet input is fed forward to enable the terminal count output (tc). the tc output thus enabled will produce a high output pulse of a duration approximately equal to a high level output of q 0 . this pulse can be used to enable the next cascaded stage. the maximum clock frequency for the cascaded counters is determined by the cp to tc propagation delay and cep to cp set-up time, according to the following formula: f max = 1 t p(max) (cp to tc) t + su (cep to cp) -------------------------------------------------------------------------------------------------- - quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns symbol parameter conditions typical unit hc hct t phl / t plh propagation delay cp to q n cp to tc mr to q n mr to tc cet to tc c l = 15 pf; v cc =5 v 19 21 20 20 10 20 24 25 26 14 ns ns ns ns ns f max maximum clock frequency 44 45 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 33 35 pf notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v
december 1990 3 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 ordering information see 74hc/hct/hcu/hcmos logic package information . pin description pin no. symbol name and function 1 mr asynchronous master reset (active low) 2 cp clock input (low-to-high, edge-triggered) 3, 4, 5, 6 d 0 to d 3 data inputs 7 cep count enable input 8 gnd ground (0 v) 9 pe parallel enable input (active low) 10 cet count enable carry input 14, 13, 12, 11 q 0 to q 3 ?ip-?op outputs 15 tc terminal count output 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 function table note 1. the tc output is high when cet is high and the counter is at terminal count (hhhh). h = high voltage level h = high voltage level one set-up time prior to the low-to-high cp transition l = low voltage level i = low voltage level one set-up time prior to the low-to-high cp transition q = lower case letters indicate the state of the referenced output one set-up time prior to the low-to-high cp transition x = dont care - = low-to-high cp transition operating mode inputs outputs mr cp cep cet pe d n q n tc reset (clear) l x x x x x l l parallel load h h - - x x x x i i i h l h l (1) count h - h h h x count (1) hold (do nothing) h h x x i x x i h h x x q n q n (1) l fig.4 functional diagram.
december 1990 5 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 fig.5 state diagram. fig.6 typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.
december 1990 6 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 fig.7 logic diagram.
december 1990 7 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 61 22 18 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 fig.8 t phl / t plh propagation delay cp to tc 69 25 20 215 43 37 270 54 46 325 65 55 ns 2.0 4.5 6.0 fig.8 t phl propagation delay mr to q n 63 23 18 210 42 36 265 53 45 315 63 54 ns 2.0 4.5 6.0 fig.9 t phl propagation delay mr to tc 63 23 18 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 fig.9 t phl / t plh propagation delay cet to tc 33 12 10 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.10 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 figs 8 and 10 t w clock pulse width high or low 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.8 t w master reset pulse width; low 80 16 14 19 7 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.9 t rem removal time mr to cp 100 20 17 19 7 6 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.9 t su set-up time d n to cp 80 16 14 25 9 7 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.11 t su set-up time pe to cp 100 20 17 30 11 9 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.11
december 1990 8 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 t su set-up time cep, cet to cp 170 34 29 47 17 14 215 43 37 255 51 43 ns 2.0 4.5 6.0 fig.12 t h hold time d n , pe, cep, cet to cp 0 0 0 - 14 - 5 - 4 0 0 0 0 0 0 ns 2.0 4.5 6.0 figs 11 and 12 f max maximum clock pulse frequency 4.6 23 27 13 40 48 3.6 18 21 3.0 15 18 mhz 2.0 4.5 6.0 fig.8 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
december 1990 9 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf input unit load coefficient mr 0.95 cp 1.10 cep 0.25 d n 0.25 cet 0.75 pe 0.30 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp to q n 23 43 54 65 ns 4.5 fig.8 t phl / t plh propagation delay cp to tc 28 48 60 72 ns 4.5 fig.8 t phl propagation delay mr to q n 29 46 58 69 ns 4.5 fig.9 t phl propagation delay mr to tc 30 51 64 77 ns 4.5 fig.9 t phl / t plh propagation delay cet to tc 17 35 44 53 ns 4.5 fig.10 t thl / t tlh output transition time 7 15 19 22 ns 4.5 figs 8 and 10 t w clock pulse width high or low 16 7 20 24 ns 4.5 fig.8 t w master reset pulse width; low 20 10 25 30 ns 4.5 fig.9 t rem removal time mr to cp 20 6 25 30 ns 4.5 fig.9
december 1990 10 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 t su set-up time d n to cp 18 8 23 27 ns 4.5 fig.11 t su set-up time pe to cp 30 17 38 45 ns 4.5 fig.11 t su set-up time cep, cet to cp 40 17 50 60 ns 4.5 fig.12 t h hold time d n , pe, cep, cet to cp 0 - 7 0 0 ns 4.5 figs 11 and 12 f max maximum clock pulse frequency 23 41 18 15 mhz 4.5 fig.8 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
december 1990 11 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 ac waveforms fig.8 waveforms showing the clock (cp) to outputs (q n , tc) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.9 waveforms showing the master reset ( mr) pulse width, the master reset to output (q n , tc) propagation delays and the master reset to clock (cp) removal time. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.10 waveforms showing the input (cet) to output (tc) propagation delays and output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.
december 1990 12 philips semiconductors product speci?cation presettable synchronous 4-bit binary counter; asynchronous reset 74hc/hct161 package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.11 waveforms showing the set-up and hold times for the input (d n ) and parallel enable input pe. the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.12 waveforms showing the cep and cet set-up and hold times. the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.

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